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STMicroelectronics Data Brief & Engineering Specification
DocID 13587 Rev 17
Page 1 of 118
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1. Core Architecture & Feature Matrix
- ARM® 32-bit Cortex®-M3 CPU Core: 72 MHz maximum frequency, 1.25 DMIPS/MHz (Dhrystone 2.1) performance at 0 wait state memory access.
- Memories: 64 to 128 Kbytes of Flash memory, 20 Kbytes of SRAM with hardware parity check.
- Clock, reset and supply management: 2.0 to 3.6 V application supply and I/Os, POR, PDR, and programmable voltage detector (PVD).
- Low-power modes: Sleep, Stop and Standby modes. VBAT supply for RTC and backup registers.
- 2 × 12-bit, 1 µs A/D converters (up to 16 channels): Conversion range: 0 to 3.6 V, dual-sample and hold capability.
- DMA Controller: 7-channel DMA controller supported peripherals: timers, ADCs, SPIs, I2Cs and USARTs.
2. Device Summary & Electrical Ratings
| Symbol | Ratings | Min | Max |
|---|---|---|---|
| VDD - VSS | External main supply voltage | -0.3 V | 4.0 V |
| VIN | Input voltage on five-volt tolerant pins | VSS - 0.3 | 5.5 V |
| TJ | Maximum junction temperature | -40 °C | +125 °C |
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Hardware Architecture Specs
Core Architecture
ARM Cortex-M3
Max Frequency
72 MHz
Flash Memory
64 KB
SRAM Cache
20 KB